1. Field of the Invention
The present invention relates to power evaluation of an electronic circuit design. More particularly, the present invention relates to a power evaluation system and a power evaluation tool that use simple arcs for calculating the power dissipation of an electronic circuit design under simulation.
2. Background
Power evaluation of integrated circuits (ICs), such as calculating on-chip power dissipation of logic circuits, has become more important, in part, due to the growing number of mobile products and the need to determine "hot spots" on ICs early in the design stage. Also, power evaluation has become much more complex since the increases in die size, speed (even though feature size and/or voltage supply may decrease), and device count of ICs has greatly complicated the task of optimizing power dissipation.
The ability to accurately evaluate, predict, and optimize power dissipation of an IC, or cells within the IC, enables designers to design better products. Power dissipation is a major issue in mobile products by virtue of the battery driven nature of such products, with lower power consumption resulting in longer battery life per charge. Low power dissipation also means lower package and die costs. In high performance computer products, power dissipation is a major concern since excessive power consumption, either by heat or by electro-migration, can damage a chip. Thus, there has been an increase in the reliance and use of power analysis tools to aid in the fabrication of ICs using traditional fabrication design tools.
The term EDA (Electronic Design Automation) as used herein includes all design automation tools that facilitate the design of an electronic circuit at the behavior, register, gate-level transistor and/or layout levels.
Also, the term cell is intended to include circuit portions within an IC that can be identified as discrete structures providing a function. For example, depending on the level of abstraction used to model a cell, the term may include structures defined at the physical level such as a transistor; at the gate/logic level such as a NAND or OR gate; or at the macro level such as a simple adder or flip-flop. The level of abstraction used depends on the design cycle stage and the speed at which modeling needs to be completed, among other things. Design automation tools that generate cell models at higher levels of abstraction tend to run faster but have a relatively greater margin of error, while such models using lower levels of abstraction tend to run slower but have a relatively lower margin of error.
Power dissipation within a cell has two fundamental components--dynamic and static power dissipation. Dynamic power dissipation is the amount of power expended by a cell in response to at least one input signal transitioning from one switching threshold to another (input signal transition) and which may also result in at least one output signal transition from one switching threshold to another within a given time period. For example, an input signal going from high to low, or vice versa, is defined as an input signal transition. Static power dissipation is the power dissipated due to current flowing from Vdd to ground such as when no signals are switching from one logic state or another. Thus, dynamic power dissipation is a function of circuit switching activity and the state of the cell, while static power dissipation is only a function of the logic state of the circuit.
The focus of the following invention is on dynamic power dissipation rather than static power dissipation since dynamic power dissipation represents a much larger portion of the total power dissipation of a typical logic circuit.
Dynamic power dissipation comprises a charge/discharge power component due to capacitive load and a short-circuit power component due to the effect of non-ideal switches that cannot be turned on and off instantaneously. As discussed in "On-Chip Power Evaluation Methods and Issues," by authors Amir Zarkesh and Wolfgang Roethig, published in the proceedings of the session entitled "On-chip Systems Design Conference," Design Supercon 97, page S141-S141-33, ISDN: 0-1933217-29-3,the energy dissipated for a charge of capacitance can be expressed with the equation below, where E is the total energy dissipated for a given capacitance C and voltage Vdd. EQU E=1/2*C*Vdd
Therefore, the charge/discharge power consumed by a driver of a signal switching circuit with frequency f is: EQU P=f*[1/2*C*Vdd].
For circuits that do not switch at a constant frequency f, an effective frequency, f_eff may be introduced. The effective frequency is the basic switching frequency multiplied with an activity factor, act, and is shown by the following equation: f_eff=f* act.
Table 1 below shows the activity factors for certain types of cell activities.
TABLE 1 Signal Activity Factor Clock 2 Counter LSB 1 Random Data 0.5 Reset Approx. 0
FIG. 1 is a schematic diagram showing a capacitive output load seen by the output pin of a driving cell in an example electronic circuit. For example, the capacitive output load seen by an output pin 2 at driving cell 4 includes cell load 6 and wire load 8. Cell load 6 includes all input pin capacitances of cells driven by driving cell 4, such as input pin capacitances 10a through 10n in cells 12a through 12n , respectively. Wire load 8 is the sum of the effective capacitance of net 14 to which output pin 2 is attached.
Measuring the cell load of driven cells may be accomplished through design automation modeling. Wire load may be measured through parasitic extraction if the wire load is calculated at the post-layout state. Parasitic extraction is known in the art. Both self capacitance to Vdd and Vss, and mutual capacitance to other signal interconnect wires also must be taken into account when measuring wire load.
Short-circuit power is proportional to the effective frequency f_eff since short circuit power always occurs concurrently with dynamic power and is dependent on the short circuit current path of a cell. As known in the art, characterization by accurate simulation is one method of modeling short circuit power in a cell.
Analyzing the power dissipation in an electronic circuit having multiple and/or different structures or cells, requires differentiating between external and internal cell power dissipation. External power may be defined as the power dissipated due to an external load, while internal power consists of short circuit power plus charge/discharge power dissipated by internal cell capacitances. Thus, in an electronic circuit having multiple cells or stages, both charge/discharge power and short circuit power in every cell must be calculated to determine the total power dissipation of the circuit. Since short circuit power of internal states of a cell depends on internal input slew rates rather than on primary input slew rates, and since the capacitive load is only seen by the last stage, the slew rate and load dependency of internal power is somewhat decoupled. The first stage is affected by the input slew rate (its load is a constant internal capacitance), and the last stage is affected by the external load seen by the last stage (since the last stage's input slew rate is an internal slew rate weakly affected by the primary input slew rate).
As known in the art, the term "slew rate" is defined as the rate of change of a voltage signal that changes from one signal value to another signal value over-time, such as a logic transition that changes from a logic LOW state to a logic HIGH state, or vice versa.
Power dissipation in sequential cells, such as a basic latch or flip-flop, is discussed below. A basic latch consumes power, if an input switches while the latch is transparent. If the latch is blocked, the switching input causes no power consumption. A flip-flop consists of basic master and slave latches in addition to an input buffer and a clock buffer. Therefore, power is consumed whenever the input or the clock signal switches. If the input switches while the clock is low, the master stage is transparent and thus, will consume power as well. On the rising edge of the dock, data is transferred from master to slave. Hence the slave and the output buffer will consume power, if the new output data is different from the old output data. On the falling edge of the clock, data is transferred from the input buffer to the master latch. Hence, the master latch consumes power if the new input data is different from the old stored data.
Sources of Dynamic Power Dissipation in a Cell
As pointed out above, short circuit currents and currents due to transient signals, such as switching transitions between logic states, are the main sources of power dissipation in a cell. For deep submicron designs, wire load tends to become more important than cell load in the case of random logic where the wires can be routed all around the chip. For data path structures with regular layout, both wire load and cell load scale down in essentially the same way. The overall ratio between load and short circuit current is almost unaffected, since both slew rate and load scale down in deep submicron design. However, the design style chosen has a major impact on the transient load current versus short circuit current. For example, optimally sized buffers exhibit both better performance and less power. For low threshold devices, static leakage current tends to increase, but is not of a significant amount compared to the dynamic power dissipated by such devices.
The switching activity component of dynamic power dissipation, which is predominant in logic and flip-flops, is more difficult to estimate, model and characterize than short circuit current. Currently, only simulation-based tools with accurate timing models can give a good picture of the power dissipated as a function of the input stimulus. Power optimization techniques in later design stages need to be able to reduce this part of the power consumption locally such as at the macro cell or even gate-level stage using characterization and simulation data that may be generated using design automation tools.
Prior methods of calculating the dynamic power dissipation of a cell at the macro cell or gate level are either very simplified and not very accurate, or are accurate but unwieldy since the number of variables used for computing power dissipation is exponentially proportional to the number of input and output pins used in the cell. More importantly, such prior methods are not well-suited for use with existing cell libraries that use complex arcs for cell timing information. A complex arc defines a sequence of events, such as an event X followed by events Y and Z, and is further described below.
The term "pin" is used herein to denote electrical connection points located on the boundary of the structure being modeled, such as first and second inputs 62, 64, carry-in input 66, carry-out output 68, and sum output 70 in a full adder like that shown in FIG. 2A, or such as the pins found in a NAND gate having two logical inputs (two input pins) and one logic output (one output pin)
A Simplified Linear Method for Analyzing Dynamic Power Dissipation
One prior art method of analyzing dynamic power dissipation of a cell includes using a simplified linear model to express energy dissipated as a function of the slew rate of an input signal transition asserted on the cell, the load seen by the output of the cell (output load), and the voltage swing of the input and output signal transitions. A more accurate model may be obtained by using a non-linear model that is a function of the slew rate of the input transition signal, the output load, and a characterization table having energy per transition values. As noted above, the simplified linear model is not very accurate, while the non-linear model can become very unwieldy when used to calculate the power dissipation of a cell having many input and output pins.
The energy per transition values, input slew rates, output loads, and cell state are obtained from cell modeling, as known in the art.
Non-Linear Methods for Analyzing Dynamic Power Dissipation
Under the non-linear approach, state-based modeling of the power dissipation of a cell uses input slew rates, output loads, and cell state generated from cell modeling to determine which energy per transition value is applicable for each transition analyzed. Total dynamic power dissipation of a particular cell includes calculating the energy dissipated by the cell for every pin having a state change in response to the assertion of a signal transition to one of the input pins of the cell. This approach results in an accurate model of the energy expended per transition. But the process can become very unwieldy depending on the number of input and output pins contained by a cell since it requires calculating the energy dissipated for every output state change that occurs in the cell for each rising and falling transition that can occur at each input pin of the cell.
For example, turning now to FIGS. 2A and 2B, calculating the power dissipation of a full adder 60 requires a total of four (4) energy per transition calculations per transition direction of an input signal because for each signal transition asserted for each input there can be four possible states. Specifically, an input signal transition asserted at first input 62 having a slew rate with a falling slope (a falling input signal transition direction), will require an energy per transition calculation for the possible case that:
1) second input 64 is at logic 0, carry-in input 66 is at logic 0, carry-out output 68 is at logic 0 and sum output 70 is at logic 0; PA1 2) second input 64 is at logic 0, carry-in input 66 is at logic 1, carry-out output 68 is at logic 0 and sum output 70 is at logic 1; PA1 3) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 0 and sum output 70 is at logic 1; and PA1 4) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 0. PA1 1) second input 64 is at logic 0, carry-in input 66 is at logic 0, carry-out output 68 is at logic 0 and sum output 70 is at logic 1; PA1 2) second input 64 is at logic 0, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 0; PA1 3) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 0; and PA1 4) second input 64 is at logic 1, carry-in input 66 is at logic 1, carry-out output 68 is at logic 1 and sum output 70 is at logic 1.
Another set of energy per transition calculations must also be performed for the case where an input signal transition having a rising slope is asserted at first input 62, as shown in truth table 72 of FIG. 2B which corresponds to full adder 60 in FIG. 2A. The energy per transition calculation for a rising input signal transition includes the possible case that:
Thus, as can be seen in the preceding example, each input pin in the cell which could possibly be affected by input signal transitions would require four (4) energy per transition calculations--a situation that can quickly become unwieldy as the number of output pins per cell increases.
Another known method for determining energy dissipation of a cell assumes that the energy per transition of a cell is equal to the energy dissipated by a signal transition occurring at an output for a given input signal, while all other outputs are held to a zero load.
For example, referring again to FIGS. 2A and 2B, calculating the energy dissipation for a signal transition asserted at second input 64 includes calculating the energy dissipated by a signal transitioning at sum output 70 by using the slew rate from the input signal applied at second input 64 and a load 71 seen by sum output 70 to determine the energy dissipated by the transition.
In the situation where more than one output undergoes a transition for a given input signal, the energy dissipated at each additional output transition also must be calculated. In the event that an input signal at second input 64 causes both sum output 70 and carry-out output 68 to change states, the total energy dissipated is the energy dissipated by the switching that occurs at second input 64, the switching that occurs at both outputs 68, 70 and the short-circuit energy dissipated by adder 60. In this scenario, determining the total energy dissipated requires calculating the energy dissipated due to: 1) the switching that occurs at second input 64 using a given slew rate and the resulting switching that occurs at sum output 70 having load 71, while the other remaining output, carry-out output 68 is held to have zero load at load 69; and 2) the switching that occurs at second input 64 using a given slew rate and the resulting switching that occurs at carry-out output 68 having load 69, while sum output 70 is held to have zero load at load 71. This method must also account for the double counting of short circuit and internal charge-discharge energy of the adder caused by the calculation, which is subtracted from the calculated energy dissipated by subtracting the energy dissipated by the switching of second input 64, while both outputs 68, 70 are held to have zero load at loads 69 and 71.
The above method is applicable to cells having many output pins without becoming too unwieldy to calculate because the state of the cell is not required in order to determine energy per transition values but is used simply to determine whether power dissipation that is due to two output states transitioning has occurred. However, this method is not compatible with the cell characterizations that are generated under the widely used arc-based cell modeling technique.
Arc-based Modeling under the Advance Library Format Method
Arc-based modeling, described in the reference manual entitled, "Advance Library Format for ASIC Cells and Blocks," version 0.9, published by Open Verilog International, (hereinafter, Advance Library Format reference) and, hereby incorporated by reference as if fully set forth herein, relies on a delay-based timing model of a cell to provide the necessary set of characterization variables necessary for analyzing the energy dissipation (and hence, power dissipation) of a cell. For a given set of stimuli, a delay-based timing model describes the cell's timing characteristic using complex arcs to describe a sequence of events. For example, an "input event a that is eventually followed by an output event X, output event Y, and output event Z."
An event is defined as a logic transition that occurs at a pin. For example, an input and output pin pair may have a timing characteristic that would be represented using a complex arc that is defined for a "rising edge on input pin A (first logic transition or event) which is followed by a falling edge on output pin Z (second logic transition or event)."
A complex arc is obtained from functional information that may be available for a library that describes the cell or directly from a design automation tool that generates functional information about the cell. The complex arc may include output pin load, input pin slew rate, skew between multiple switching inputs, voltage, and temperature. A complex arc may also contain state information. For example, in the delay-based timing model, a complex arc is created for each input and output pin pair in the cell for a given input pin slew rate and output pin load, while all other output pins are held to a zero load. Thus, a complex arc describes cell behavior without explicitly describing the stimuli (output pin load, and the like . . . ) applied to the cell that caused the events described by the arc.
Power characterization is a superset of cell timing characterization using the same set and range of characterization variables, including load, input slew rate, skew between multiple switching inputs, voltage, and temperature. Thus, a complex arc can provide the necessary cell characterization variables that are required to determine the power dissipated by the cell switching activity described by the arc.
The energy per transition values, input slew rates, output loads, cell state, and the like, are related to the cell's functional characteristics and may be obtained, with varying degrees of accuracy depending on the level of abstraction used, through the modeling of the cell using design automation tools discussed above. The cell is modeled to characterize the circuit's dynamic response to a given set of inputs, resulting in a set of values representing over time the circuit's performance characteristics. The cell models form a library of circuit information that give designers circuit characteristics such as capacitance (pin capacitances, transistor capacitances, interconnect capacitances, and the like), and output values of the cell in response to asserted input signals and the slew rates of such input signals to the circuit or cell. Calculating the power dissipation of the cell through energy per transition values uses these modeled characteristics.
As discussed above, energy dissipation caused by switching activity is a function of the charge/discharge current and short circuit current for a given set of cell characterization variables. Consequently, complex arcs are used, as disclosed in the Advance Library Format reference, to determine the number and type of transitions that occur for a given set of stimuli. The transitions in each complex arc can then be used to determine the energy dissipated by the cell.
The method tracks transitions (both input and output) by maintaining an event queue for each output transition that occurs for a given input transition. Also, in a case where more than one output transition occurs for a given input pin transition, the method must determine the order of occurrence for each output transition. This causes the method to maintain a variable number of queues for tracking each transition for a given input pin and for all output pins, and for determining the order of occurrence of each transition that occurs at each output pin. This is inefficient because the number of queues required to perform energy and power dissipation calculations vary according to the number of output pins that may incur a transition caused by an input transition that occurs at a cell. Thus, the method becomes inefficient very quickly when evaluating cells that have many output pins, such as a cell having more than two outputs, because a queue must be maintained for each of the output pins.
Since a complex arc that represents the case where a signal transition occurs at more than one output for a given input transition cannot accurately model the actual sequence of each output transition, the method must model each possible sequence of output pin transitions that can occur. Each possible sequence must be considered because the order of transitions occurring at the output pins cannot be predicted by cell modeling. This greatly increases the inefficiency of the method in calculating energy dissipated since an arc must be generated for each possible output transition sequence for a given input pin transition.
For example, the case where carry-out output 68 and sum output 70 transition in response to an input transition at second input 64 in full adder 60 requires the generation of two arcs to cover all possible sequences that can occur between carry-out output 68 and sum output 70; an arc where carry-out output 68 transitions first and sum output 70 transitions second; and another arc where sum output 70 transitions first and carry-out output 68 transitions second. The need to cover all possible output pin sequences exponentially increases the number of arcs that must be generated.
The increased use and importance of power analysis tools has created a need for new cell libraries. But library creation/generation is also a complex task, resulting in a need to leverage existing cell libraries by providing a power analysis tool that is compatible with EDA tools that provide widely-used cell characterizations, such as arcs, while remaining easy to implement and efficient to use.
Accordingly, there exists a need to provide a power analysis system and tool that are both accurate and efficient yet compatible with the arc-based timing methodology.